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| orderin g numbe r : ENA1760 bi-cmos lsi piezo actuator driver ic lv8491ct overview the lv8491ct is a piezoelectric actuator driver ic. it inte rnally generates drive waveforms and this makes it possible to control piezoelectric actuators with simple instructions. features ? actuators using piezoelectric elements can be driven and controlled simply by i 2 c communication. ? mu ltiple patterns of drive waveform conditions can be se t for b efore and after performing normal operation when executing the drvpulse instruction. ? the piezoelectric drive waveforms are set exte rn ally by serial input signals using the i 2 c interface. the rising and falling timings are determined with clock count. ? st artup/stop of the ic is controlled by enin register input through i 2 c communication. ? th e time for which the actuator is driven is dete rm ined with the drive frequency setting based on i 2 c communication. ? busy ou tput can be used to identify the operation/stop state of the actuator while output is present at the out pin. the b usy signal can also be checked w ith the read function controlled through i 2 c communication. ? built-in undervoltage detection and protection ci rcu it, and register power-on reset function. specifications absolute maximum ratings at ta = 25 c, gnd = 0 v parameter symbol conditions ratings unit supply voltage v cc max -0.5 to 5.0 v output current i o max 300 ma peak output current 1 i o peak 1 t 1ms 750 ma peak output current 2 i o peak 2 t 10 s 1200 ma input signal voltage v in max -0.5 to v cc +0.5 v allowable dissipation pd *mounted on a specified board. 350 mw operating temperature topr -30 to +85 c storage temperature tstg -55 to +125 c * specified board : 40mm 40mm 1.6mm, glass epoxy board. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 70710 sy pc 20100517-s00002 no.a1760-1/20
lv8491ct allowable operating conditions at ta = 25 c, gnd = 0v parameter symbol conditions ratings unit supply voltage v cc 2.2 to 3.3 v input signal voltage v in -0.3 to v cc v corresponding clk input frequency fclk to 60 mhz maximum operating frequency ct max set stp count 512 times electrical characteristics at ta = 25c, v cc = 2.8v, gnd = 0v, unless otherwise specified. ratings parameter symbol conditions min typ max unit standby mode current drain i cc 0 no clk input, when scl/sda = l 1.0 a operating mode current drain i cc 1 clk = 10mhz, when scl/sda = h 0.5 1.0 ma high-level input voltage v ih 2.2v v cc 3.3v scl, sda 1.4 v cc +0.3 v low-level input voltage v il 2.2v v cc 3.3v scl, sda -0.3 0.4 v clk pin high-level input voltage v ih 2 clk 0.5 v cc v cc +0.3 v clk pin low-level input voltage v il 2 clk -0.3 0.2 v cc v busy pin high-level output voltage b o h with no load v cc -0.15 v cc v busy pin low-level output voltage b o l with no load 0 0.15 v busy pin leakage current blk 1.0 a busy pin sink current blsk busy pin voltage when busy is set low = 2.8v 1.5 2.2 ma busy pin source current blso busy pin voltage when busy is set high = 0v 1.5 2.2 ma low voltage detection voltage vres v cc voltage 1.8 2.0 2.2 v output block upper-side on resistance ronp 0.8 1.5 output block lower-side on resistance ronn 0.6 1.2 turn on time tplh with no load *1 0.15 s turn off time tphl with no load *1 0.1 s *1 : rising time from 10 to 90% and falling time from 90 to 10% are specified with regard to the out pin voltage. package dimensions unit : mm (typ) 3399 pd max -- ta ambient temperature, ta ? c allowable power dissipation, pd max ? w 0 0.18 0.4 0.45 0.5 0.2 0.3 0.1 0.6 ? 30 ? 20 80 60 20 40 01 no.a1760-2/20 sanyo : wlp10(2.17x0.87) top view side view side view bottom view 0.22 54 3 1 2 ab 0.235 0.4 0.285 0.4 0.285 0.33 max 0.08 0.87 2.17 0 0 specified board : 50 501.6mm 3 glass epoxy lv8491ct pin assignment ball side view a 1 2 3 4 5 scl sda gnd out1 rfg clk (nc) busy v cc out2 1 2 3 4 5 bb top view a 2.17 0.4 0.4 scl clk sda (nc) gnd busy out1 v cc rfg out2 0.87 a1:scl a2:sda a3:gnd a4:out1 a5:rfg b1:clk b2:(nc) b3:busy b4:v cc b5:out2 no.a1760-3/20 lv8491ct block diagram gnd clk scl sda busy rfg out2 out1 v cc 2-wire serial interface output control startup control block piezoelectric drive waveform generation register value of the resistor connected to the rfg pin inrush current flowing to the piezoelectri c elements can be controlled in the lv 8491ct by inserting a resistor between the rfg pin and gnd potential. since the resistance affects the actuator operation, the constant must be determined in a range from 0 to 3.3 while monitoring the operation of the actuator. capacitor on the v cc line piezoelectric actuators are capacitive loads in electrical terms, and they operate units by charging and discharging the charges. since the charge be tween the capacitor on the v cc line and piezoelectric elements is transferred, the capacitor must be mounted near the v cc pin. the capacitance of the capacitor require d is determined by the capacitance of the piezoelectric element. a capacitance within a range th at does not affect operation must be selected. no.a1760-4/20 lv8491ct serial bus communication specifications i 2 c serial transfer timing conditions th1 ton ts2 th2 twh twl sda scl start condition input waveform condition stop condition ts1 ts3 th1 resend start condition tbuf tof standard mode parameter symbol conditions min typ max unit scl clock frequency fscl scl clock frequency 0 100 khz ts1 setup time of scl with respect to the falling edge of sda 4.7 s ts2 setup time of sda with respect to the rising edge of scl 250 ns data setup time ts3 setup time of scl with respect to the rising edge of sda 4.0 s th1 hold time of scl with respect to the rising edge of sda 4.0 s data hold time th2 hold time of sda with respect to the falling edge of scl 0.06 s twl scl low period pulse width 4.7 s pulse width twh scl high period pulse width 4.0 s ton scl/sda (input) rising time 1000 ns input waveform conditions tof scl/sda (input) falling time 300 ns bus free time tbuf interval between stop condition and start condition 4.7 s high-speed mode parameter symbol conditions min typ max unit scl clock frequency fscl clock frequency of scl 0 400 khz ts1 setup time of scl with respect to the falling edge of sda 0.6 s ts2 setup time of sda with respect to the rising edge of scl 100 ns data setup time ts3 setup time of scl with respect to the rising edge of sda 0.6 s th1 hold time of scl with respect to the rising edge of sda 0.6 s data hold time th2 hold time of sda with respect to the falling edge of scl 0.06 s twl scl low period pulse width 1.3 s pulse width twh scl high period pulse width 0.6 s ton scl/sda (input) rise time 300 ns input waveform conditions tof scl/sda (input) fall time 300 ns bus free time tbuf interval between the stop condition and the start condition 1.3 s no.a1760-5/20 lv8491ct i 2 c bus transfer method start and stop conditions the i 2 c bus requires that the state of sda be preserved while scl is high as shown in the timing diagram below during a data transfer operation. ts2 th2 scl sda when data is not being transferred, both scl and sda are in the high state. the start condition is generated and access is started when sda is changed from high to low while scl and sda are high. conversely, the stop condition is generated and access is e nded when sda is changed from low to high while scl is high. th1 th3 scl sda start condition stop condition no.a1760-6/20 lv8491ct data transfer and acknowledgement response after the start condition is generated, data is transferred on e byte (8 bits) at a time. any number of data bytes can be transferred consecutively. an ack signal is sent to the sending side from the receiving side every time 8 bits of data are transferred. the transmission of an ack signal is perform ed by setting the receiving side sda to low after sda at the sending side is released immediately after the clock pulse of sc l bit 8 in the data transferred has fallen low. after the receiving side has sent the ack signal, if the next byte transfer operation is to receive only the byte, the receiving side releases sda on the fa lling edge of the 9th clock of scl. there are no ce signals in the i 2 c bus ; instead, a 7-bit slave address is assi gned to each device, and the first byte of the transfer data is allocated to the 7- bit slave address and to the command (r /w) which specifies the direction of subsequent data transfer. the read function of the lv8491ct provides only the functionality to test the busy state. 7-bit address data is transferred sequentially starting at the msb and th e second and subsequent bytes are written if the state of the 8th bit is low an d read if the state is high. in the lv8491ct, the slave address is stipulated to be ?1110010.?. write mode timing m s b l s b a c k l s b a c k m s b m s b l s b a c k w scl sda 0001 1 000 0 000 0 000 1 data register address slave address start stop read mode timing l s b a c k m s b m s b l s b a c k r scl sda 1100 0 000 0 0 stop data slave address start no.a1760-7/20 lv8491ct data transfer write format the slave address and write command must be allocated to the first byte and the re gister address in the serial map must be designated in the second byte. for the third byte, data transfer is carried out to the addr ess designated by the register address which is written in the second byte. subsequently, if data continues, the register address value is automatically incremented for the fourth and subsequent bytes. thus, continuous data transfer starting at th e designated address is made possible. after the register address reaches 1fh, the transf er address for the next byte is set to 00h. data write example s 1 1 1 0 0 1 0 0 a 0 0 0 0 0 0 1 0 a data 1 a slave address register address set to 02h write data to address 02h r/w = 0 written data 2 a data 3 a data 4 a p write data to address 03h write data to address 04h write data to address 05h s start condition p stop condition a a ack signal master side transmission slave side transmission data read example s 1 1 1 0 0 1 0 1 a data a p slave address read data r/w = 1 read notify end of read by not sending out ack s start condition p stop condition a a ack signal master side transmission slave side transmission no.a1760-8/20 lv8491ct no.a1760-9/20 serial map register address data a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 m/i drvpulse [6 : 0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gate enin cksel [1 : 0] ret [1 : 0] init 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 rst [7 : 0] 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 gtas [7 : 0] 3 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 gtbr [7 : 0] 4 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 gtbs [7 : 0] 5 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 stp [7 : 0] 6 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 initmov [7 : 4] 7 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 nrpulse1 [5 : 0] 8 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 nrp-a [5 : 0] 9 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 nrp-b [5 : 0] 10 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 nrp-c [5 : 0] 11 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 nrp-d [5 : 0] 12 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 nrpulse2 [5 : 0] 13 0 0 0 0 1 1 0 1 nrp-e [5 : 0] 14 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 nrp-f [5 : 0] 15 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 nrp-g [5 : 0] 16 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 nrp-h [5 : 0] 17 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 nr1gtbr [7 : 0] 18 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 nr1gtbs [7 : 0] 19 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 nr2gtbr [7 : 0] 20 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 nr2gtbs [7 : 0] 21 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 nr3gtbr [7 : 0] 22 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 nr3gtbs [7 : 0] 23 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 upper : register name lower : default value continued on next page. lv8491ct continued from preceding page. register address data a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 nr4gtbr [7 : 0] 24 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 nr4gtbs [7 : 0] 25 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 nr5gtbr [7 : 0] 26 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 nr5gtbs [7 : 0] 27 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 busy 28 read mode only register 0 0 0 0 0 0 0 0 upper : register name lower : default value nr drive pulse output rise operation no.a1760-10/20 nr1 waveform nr2 nr3 nr5 steady-state waveform out output busy output number of periods set by nrp-a nr start waveform (no ga te_b output generated) one period nrp-b nrp-c nrp-d drvpulse communication input number of periods set by nrpulse1 + 1 nr4 for example, when nrpulse1 is set to 15, nrp-a to 3, nrp- b to 6, nrp-c to 9, and nrp-d to 12, one period of the nr start waveform (no gate_b output) is output, followed by three periods of the nr1 waveform, three periods of the nr2 waveform, three periods of the nr3 waveform, three periods of the nr4 waveform, three periods of the nr5 waveform, and then stp x drvpulse periods of the steady-state waveform. when nrpulse1 is set to 0, no nr pulse is generated and the same output as the normal drvpulse input is generated. in addition, when nrp-a and nrp-b are set the same value, the nr2 waveform is not out put, and the nr3 waveform is output following the nr1 waveform. fall operation nr5 nr4 nr3 nr1 steady-state waveform out output busy output nrp-e nrp-f nrp-g nrp-h number of periods set by nrpulse2 nr2 the fall waveforms are output in order from the nr5 waveform to the nr1 waveform. the switching timing is set in the same manner as that for rise operation. lv8491ct nr drive waveform settings the settings are the same as those for the normal drive waveform. drive waveforms are generated using the same parameters as the normal waveform for rst and gtas, and the nr waveform setting values for gtbr and gtbs. example: nr1 waveform rst = number of clock pulses per period - 1 waveform start reference point gtas= ta+1 nr1gtbr= gtas+off nr1gtbs= nr1gtbr+tb rises after two clock pulses from the reference. the waveforms start after two clock pulses, so ta-1+2 = ta+1. nr start waveform nr waveform output control is as follows. when nrpulse1 is set, a waveform without gate_b output is output in the first rise period. after that the waveforms set by nr are output in order from nr1. when there are no nr settings for rise operation (whe n nrpulse = 0), the nr start waveform is not output. the same parameters as those of the normal waveform are referenced for rst and gtas, and gtbr and gtbs are zero input waveforms. rst = number of clock pulses per period - 1 waveform start reference point gtas= ta+1 rises after two clock pulses after from the reference. gate_b is not output the waveforms start after two clock pulses, so ta-1+2 = ta+1. no.a1760-11/20 lv8491ct no.a1760-12/20 serial mode settings 0 0 0 0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 d0 to d6: drvpulse [6 : 0] operation count setting register. specify a number from 0 to 127. the number of cyclic operations determined by lv8491ct 2 0 0 0 0 0 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 rst7 to rst0 : specifies the number of clocks per period (0 to 255). default = 0 3 0 0 0 0 0 0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 gtas7 to gtas0 : sets the gate_a pulse set value (0 to 255). default = 0 4 0 0 0 0 0 1 0 0 d7 d6 d5 d4 d3 d2 d1 d0 gtbr7 to gtbr0 : sets the gate_b pulse reset value (0 to 255). default = 0 5 0 0 0 0 0 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 gtbs7 to gtbs0 : sets the gate_b pulse set value (0 to 255). default = 0 rst7-0 gtas7-0 gtbr7-0 gtbs7-0 gatea gateb 6 0 0 0 0 0 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 stp7 to stp0 : specifies the number of output pulse steps with regard to drive input (1 to 256). default = 1 the setting value range is handled as the data value plus 1. when data is input in 8-bit units (0 to 255), it is handled as an stp period of 1 to 256. no.a1760-13/20 lv8491ct no.a1760-14/20 7 0 0 0 0 0 1 1 1 0 0 0 0 d3 d2 d1 d0 initmov7 to initmov4 : sets the number of swing back of the initialization sequence to be performed (16 to 256). default = 16 d3 d2 d1 d0 init7 to 4 16 to 256 0 0 0 0 0 16 0 0 0 1 1 32 0 0 1 0 2 48 0 0 1 1 3 64 0 1 0 0 4 80 0 1 0 1 5 96 0 1 1 0 6 112 0 1 1 1 7 128 1 0 0 0 8 144 1 0 0 1 9 160 1 0 1 0 10 176 1 0 1 1 11 192 1 1 0 0 12 208 1 1 0 1 13 224 1 1 1 0 14 240 1 1 1 1 15 256 8 0 0 0 0 1 0 0 0 0 0 d5 d4 d3 d2 d1 d0 nrpul15 to nrpul10: 0 to 63. default = 0 specifies the total number of output periods of the nr1 to nr5 drive waveforms during rise operation when multiple drive waveforms are output continuously during actuator operation. when set to 0, nr drive waveforms are not output during rise operation, and normal output operation is performed. 9 0 0 0 0 1 0 0 1 0 0 d5 d4 d3 d2 d1 d0 nrp-a5 to nrp-a0: 0 to 63. default = 0 this register specifies the first switching timing of the rise nr drive waveform. it determines the number of nr1 waveform output periods during rise operation. 10 0 0 0 0 1 0 1 0 0 0 d5 d4 d3 d2 d1 d0 nrp-b5 to nrp-b0: 0 to 63. default = 0 this register specifies the second switching timing of the rise nr drive waveform. the nr2 waveform is output for a number of period s equal to the difference between nrp-a and nrp-b. 11 0 0 0 0 1 0 1 1 0 0 d5 d4 d3 d2 d1 d0 nrp-c5 to nrp-c0: 0 to 63. default = 0 this register specifies the third switching timing of the rise nr drive waveform. the nr3 waveform is output for a number of period s equal to the difference between nrp-b and nrp-c. lv8491ct no.a1760-15/20 12 0 0 0 0 1 1 0 0 0 0 d5 d4 d3 d2 d1 d0 nrp-d5 to nrp-d0: 0 to 63. default = 0 this register specifies the fourth switching timing of the rise nr drive waveform. the nr4 waveform is output for a number of periods equal to the difference between nrp-c and nrp-d, and the nr5 waveform is output for a number of periods equal to the difference between nrp-d and nrpul1. when setting the rise nr drive waveforms, the setting values should in principle satisfy the following relationship. nrp-a nrp-b nrp-c nrp-d (when this relationship is not satisfied, unintended drive wave forms may be output. however, this will not result in ic breakdowns or other damage.) 13 0 0 0 0 1 1 0 1 0 0 d5 d4 d3 d2 d1 d0 nrpul25 to nrpul20: 0 to 63. default = 0 specifies the total number of output periods of the nr5 to nr1 drive waveforms during fall operation, when multiple drive waveforms are output continuously during actuator operation. when set to 0, nr drive waveforms are not output during fall operation, and operation stops. 14 0 0 0 0 1 1 1 0 0 0 d5 d4 d3 d2 d1 d0 nrp-e5 to nrp-e0: 0 to 63. default = 0 this register specifies the first switching timing of the fall nr drive waveform. it determines the number of nr5 waveform output periods during fall operation. 15 0 0 0 0 1 1 1 1 0 0 d5 d4 d3 d2 d1 d0 nrp-f5 to nrp-f0: 0 to 63. default = 0 this register specifies the second switching timing of the fall nr drive waveform. the nr4 waveform is output for a number of periods equal to the difference between nrp-e and nrp-f. 16 0 0 0 1 0 0 0 0 0 0 d5 d4 d3 d2 d1 d0 nrp-g5 to nrp-g0: 0 to 63. default = 0 this register specifies the third switching timing of the fall nr drive waveform. the nr3 waveform is output for a number of period s equal to the difference between nrp-f and nrp-g. 17 0 0 0 1 0 0 0 1 0 0 d5 d4 d3 d2 d1 d0 nrp-h5 to nrp-h0: 0 to 63. default = 0 this register specifies the fourth switching timing of the fall nr drive waveform. the nr2 waveform is output for a number of period s equal to the difference between nrp-g and nrp-h, and the nr1 waveform is output for a number of periods equal to the difference between nrp-h and nrpul2. when setting the fall nr drive waveforms, the setting values should in principle satisfy the following relationship. nrp-e nrp-f nrp-g nrp-h (when this relationship is not satisfied, unintended drive wave forms may be output. however, this will not result in ic breakdowns or other damage.) lv8491ct no.a1760-16/20 18 0 0 0 1 0 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 nr1gtbr7 to nr1gtbr0: 0 to 255. default = 0 gate_b pulse reset value for nr1 waveform 19 0 0 0 1 0 0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 nr1gtbs7 to nr1gtbs0: 0 to 255. default = 0 gate_b pulse set value for nr1 waveform 20 0 0 0 1 0 1 0 0 d7 d6 d5 d4 d3 d2 d1 d0 nr2gtbr7 to nr2gtbr0: 0 to 255. default = 0 gate_b pulse reset value for nr2 waveform 21 0 0 0 1 0 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 nr2gtbs7 to nr2gtbs0: 0 to 255. default = 0 gate_b pulse set value for nr2 waveform 22 0 0 0 1 0 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 nr3gtbr7 to nr3gtbr0: 0 to 255. default = 0 gate_b pulse reset value for nr3 waveform 23 0 0 0 1 0 1 1 1 d7 d6 d5 d4 d3 d2 d1 d0 nr3gtbs7 to nr3gtbs0: 0 to 255. default = 0 gate_b pulse set value for nr3 waveform 24 0 0 0 1 1 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 nr4gtbr7 to nr4gtbr0: 0 to 255. default = 0 gate_b pulse reset value for nr4 waveform 25 0 0 0 1 1 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 nr4gtbs7 to nr4gtbs0: 0 to 255. default = 0 gate_b pulse set value for nr4 waveform 26 0 0 0 1 1 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 nr5gtbr7 to nr5gtbr0: 0 to 255. default = 0 gate_b pulse reset value for nr5 waveform 27 0 0 0 1 1 0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 nr5gtbs7 to nr5gtbs0: 0 to 255. default = 0 gate_b pulse set value for nr5 waveform 28 no register address d7 0 0 0 0 0 0 0 read only register line. d7 : busy register set to 1 when th e ic is performing the output operation. set to 0 when the ic stops the output operation. lv8491ct functional description 1 period : one period of out waveform operation is equivalent to one output operation. tf = 1 period initialization sequence (on or off and direction can be set by i 2 c) : this is an internal sequence in which the actuator is moved to the initial position when the ic is started up. switching the value of enin regist er from 0 to 1 starts the ic. the presence or absence of the initialization operation can be set using the initialization mode select register (init). if the initialization operation is specified, the direction of th e initialization sequence can be set using the m/i register. ? m/i register = 0 : initialization processing in infinity direction the ic performs the number of operations determined by stp setting period init setting times in the infinite direction, then waits for the period equivalent to stp se tting period 4 times, and performs the number of swing back operations equal to stp setting period ret setting times in the macro direction. ? m/i register = 1 : auto macro operation in macro direction the ic performs the number of operations determined by stp setting period init setting times in the macro direction, then waits for the period equivalent to stp setting periods 4, and performs the number of swing back operations equal to stp period setting period ret setting times in the infinity direction. clk input : the input pin for the external clk input that provides the reference time for generating drive waveforms. the frequency divi sion ratio for i 2 c communication can be selected from 1/4, 1/2, and 1/1. drive waveforms are generated by counting this frequency-divided clk pulses as the basic count unit. the lv8491ct supports frequency range of 10mhz to 60mhz depending on the frequency division ratio and counter settings. register setting sequence example (1) apply v cc . (2) set up the register address 0x01 to 0x07 (setting up waveform and drive conditions) (3) set the enin register to 1 (initialization startup when the initialization sequence is enabled, or ic startup). (4) af operation starts (actuator operation instruction) according to the m/i and drvpulse settings. i 2 c communication during output operation i 2 c communication is possible to all registers during ic operation (during out output or when busy is high). however, note that when drive waveform settings are changed during actuator or other operation, unintended waveforms may be output. no.a1760-17/20 lv8491ct actuator drive waveform settings : configuration of piezoelectric actuator drive waveform no.a1760-18/20 drive parameter settings f = 1 period ta tb off rst = number of clock pulses in period minus 1 gtas = ta + 1 gtbr = gtas + off gtbs = gtbr + tb waveform start reference point rises here after two clock pulses from reference. ta-1+2 = ta+1 since the waveforms start after two clock pulses. since the counter starts from zero, a value minus 1 is set. the drive waveforms are set using four parameters: rst, gtas, gtbr and gtbs. rst : parameter determines the period, and sets the reference clock pulse count minus 1. gtas : parameter determines the time taken for the gate signal a to the falling edge from the reference point. since the signal raises after two clock pulses from the reference, the ta reference clock cycle count plus 1 is set. gtbr : parameter determines the time taken for the gate si gnal b to the rising edge from the reference point. it sets the value obtained by adding the reference clock pulse count during the time from gtas to ?off.? gtbs : parameter determines the time taken for the gate si gnal b to the falling ewdge from the reference point. it sets the value obtained by adding the reference clock pulse count during the time from gtbr to ?tb.? [example of settings] when setting reference clock to 10mhz, period to 13 s, ta to 2.0 s, off to 0.3 s, and tb to 3.0 s since the reference clock time is 0.1 s : the period is 130 clks. specify 129 (rst value of 130 -1). ta is 20 clks. specify 21 (gtas value of 20 + 1). off is 3 clks. specify 24 (gtbr value of 21 + 3). tb is 30 clks. specify 54 (gtbs value of 24 + 30). lv8491ct timing charts enlarged view of the sequence of output signals (rst setting + 1) number of clock pulses (rst setting + 1) number of clock pulses (gtas setting - 1) number of clock pulses (gtas setting - 1) number of clock pulses (gtas setting - 1) number of clock pulses (gtas setting - 1) number of clock pulses (gtas setting - 1) number of clock pulses out1 operation toward infinity operation toward macro out2 (gtbr setting -1) number of clock pulses (gtbr setting -1) number of clock pulses (gtbs setting - 1) number of clock pulses out1 out2 sequence of initial setting operation (?on? or ?off? can be set by the serial settings.) when m/i register = 00 movement toward infinity position no.a1760-19/20 when m/i register = 01 movement toward macro position out1 enin register operation toward infinity standby state standby state operation toward macro out2 busy register startup or initialization sequence start when enin is set to 1 busy output is high during initial setting operation. high during initial setting in wait state too busy output is low after initial setting. busy output is high during initial setting operation. high during initial setting in wait state too busy output is low after initial setting. out1 enin register operation toward macro operation toward infinity out2 busy register startup or initialization sequence start when enin is set to 1 stp period init times stp period 4 1 period 1 period stp period ret setting times stp period init times stp period 4 stp period ret setting times initial setting operation time initial setting operation time lv8491ct sequence of operations triggered by drvpulse input out1 m/i register state ps no.a1760-20/20 gate setting output logic this catalog provides information as of july, 2010. specifications and informat ion herein are subject to change without notice. dr vpulse setting en infinity direction logic selection operation toward macro operation toward infinity (stp setting period 2 times) out2 busy busy register is set to 1 only during operation returns to high when enin is set to 0, even in the middle of operation. equivalent to 2 pulses = stp setting period operation for 2 times serial communication of operation instruction completed. 00000000_00000010 (operation 2 times toward infinity) i 2 c communication operation instruction completed 00000000_10000010 (operation 2 times toward macro) macro direction logic selection operation stops when enin is set to 0. 1 period i 2 c communication operation starts on completion of drvpulse input. on out2 out1 forward off onoff out1 out2 reverse wait wait gate mode2 : forward, wait, reverse 1 period out1 out2 forward forward forward forward reverse braking braking ga te mode1 : forward, braking, reverse 1 period on out2 out1 reverse output mode off onoff on out2 out1 braking off on off out2 out1 wait off offoff off sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. |
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